发明名称 SYSTEM FOR DETECTING FAULT OF BUS IN MULTIPROCESSOR SYSTEM
摘要 PURPOSE:To apply a processing for a fault before a fixed fault is generated and to perform a stable operation, by detecting an intermittent faulty part before the fixed fault at a bus loop is generated without affecting on an operating system. CONSTITUTION:Plural processors 2-5 are connected to a loop-shaped bus 1 in a bus fault detecting system, and the processor 2 is set as a re-sending number of times tabulating processor which performs the reception of information uniformly from all of the processors. Also, the upstream transmission processor 4 is connected to the processor 2, and the downstream transmission processor 5 is connected to the processor 2 via the fault processor 3. The loss of an information frame is generated intermittently at the position of the processor 3 from the flow of the information on the bus 1. And the information is sent from the transmission processor to an reception processor, and a response from the reception processor is confirmed, and when no response is obtained, re-sending are performed from each of the processors 4 and 5, and the number of times of re-sending is tabulated, thereby, the processor at the faulty part can be detected from the distribution state of the number of times of resending.
申请公布号 JPS63158939(A) 申请公布日期 1988.07.01
申请号 JP19860307355 申请日期 1986.12.23
申请人 NEC CORP 发明人 KASAGI SHINJI
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