发明名称 DEPLETION MODE FET LOGIC SYSTEM
摘要 <p>DEPLETION MODE FET LOGIC SYSTEM A GaAs D-MESFET logic system having a low power delay product has a switching section and a voltage level shifting section. The voltage level shifting section consists of a chain of diodes and a pulldown transistor. The switching section consists of an array of D-MESFETs which acts to speed up operation of a coupling capacitor. The low power dissipation of known capacitor coupled D-MESFET logic is thus preserved, while reducing gate delay. 12</p>
申请公布号 CA1244529(A) 申请公布日期 1988.11.08
申请号 CA19850490852 申请日期 1985.09.16
申请人 NORTHERN TELECOM LIMITED 发明人 SITCH, JOHN E.
分类号 H03K19/0185;H01L21/8222;H01L27/08;H01L27/082;H01L27/095;H01L29/80;H03K19/00;H03K19/017;H03K19/094;H03K19/0952;(IPC1-7):H03K19/017 主分类号 H03K19/0185
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