| 摘要 |
PURPOSE:To easily detect a fault without a decrease in integration degree nor an increase in the number of test terminals by composing a scan path type FF by using scan path type dedicated transistors (TR). CONSTITUTION:The gate array consists of an internal area 2 provided on a base 1 and four input/output buffer parts 3 composed of two-way buffers or tri-state buffers. The internal area 2 includes a cell array 4 and a dedicated TR area 5 which constitutes the scan path FF circuit where FFs 1 correspond to the kinds of enable signals, one to one. Here, when clock pulses as many as the kinds of enable signals are inputted to the scan path FF, all the enable signals are outputted. Those are inputted to a memory tester to easily conduct a fault test without any decrease in integration degree. |
