PROCESS FOR IDENTIFYING PERIPHERAL DEVICES

摘要

Process for identifying peripheral devices within a digital communication system, in particular a message routing installation, centrally controlled by a central data processor and having as party and line record several decentralized input and output processors equipped with a memory which control the peripheral devices. Each processor is connected to the central data processor through a peripheral interface device. A record address (SA), a record type (ST) and a memory capacity identification code for the peripheral device are transmitted via the interface device (PBC) to the central data processor, which then transmits a memory load information for each record in the form of a memory load retrieval signal via the data bus (DBUS) to the interface device (PBC) and hence to the memory (SRM). The process is used to identify peripheral devices in respect of availability and performance within the communication system.