Point synchronization generating circuit for television display and its use for symbol incrustation

摘要

The circuit disclosed provides for operation in wide ranges of temperature with high temporal stability. It comprises a quartz clock providing the point frequency, a delay circuit with N outputs to delay the clock signal by 1 to N increments with a value 1/NFP from one output to the following one. A decoding and control logic circuit receives the N shifted signals ad the external line synchronization and codifies the rank of the first shifted signal which follows the line synchronization. A selection logic circuit controlled by this information on rank selects the corresponding output.