| 摘要 |
PURPOSE:To detect the duty abnormality and the frequency abnormality of a reference clock by generating a pulse for clock abnormality detection which has the phase synchronized with that of the reference clock and has a potential opposite to that of the reference clock and has the pulse length shorter than the reference clock. CONSTITUTION:A fixed oscillator 11 of a DPLL 1 oscillates a digital pulse having integer-fold frequency of the reference clock, and a counting part 12 counts this pulse and sends a phase comparison signal at each time of counting a certain number. A clock reference detection pulse generating means 2 takes the counted value outputted from the counting part 12 as the input to generate the pulse for clock abnormality detection, which has the logic opposite to that of the reference clock and whose pulse length is shorter than that of the reference clock by one or several periods of the oscillation frequency of the oscillator 11, and outputs this pulse to a clock abnormality detecting means 3. The means 3 takes the pulse for clock abnormality detection and the reference clock as the input to operate them in an OR circuit and outputs the result. Thus, the occurrence of glitch is detected, and the duty abnormality and the frequency abnormality of the reference clock are detected. |
