发明名称 |
Elimination of STI recess and facet growth in embedded silicon-germanium (eSiGe) module |
摘要 |
A method (and semiconductor device) of fabricating a semiconductor device eliminates shallow trench isolation (STI) recess in embedded SiGe p-type field effect transistor (pFET) structures. This increases device performance by improving isolation and decreasing leakage current caused by SiGe facet growth and silicide encroachment at the STI. A mask is selectively formed over the STI and adjacent nFET regions to protect them during formation (e.g., reactive ion etching (RIE)) of the embedded source/drain (S/D) regions of the pFET. The mask also extends over the STI edge by a predetermined distance to cover a portion of the embedded S/D region disposed between the STI and gate structure. This helps protect or isolate the STI region during SiGe layer formation in the defined embedded S/D regions.
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申请公布号 |
US2009184341(A1) |
申请公布日期 |
2009.07.23 |
申请号 |
US20080009204 |
申请日期 |
2008.01.17 |
申请人 |
CHARTERED SEMICONDUCTOR MANUFACTURING, LTD. |
发明人 |
CHONG YUNG FU;TEO LEE WEE;TAN SHYUE SENG;TAN CHUNG FOONG |
分类号 |
H01L27/092;H01L21/8238 |
主分类号 |
H01L27/092 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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