A system that includes multiple modules of an integrated circuit; a network on chip that is coupled to the multiple modules; a bus, coupled in parallel to the network on chip to the multiple modules; wherein a latency of the bus is lower and more predictable than an average latency of the network of chip.
申请公布号
WO2009072134(A3)
申请公布日期
2009.07.23
申请号
WO2008IL01589
申请日期
2008.12.07
申请人
TECHNION RESEARCH & DEVELOPMENT FOUNDATION LTD;CIDON, ISRAEL;KOLODNY, AVINOAM;WALTER, (ZIGMOND) ISASK'HAR
