| 摘要 |
A mixed-mode signal processor includes a first summer having a first input that receives a first analog signal, a second input and an output that supplies a second analog signal. A decision circuit outputs a digital signal based on the second analog signal. A mixed-mode decision feedback equalizer (DFE) includes a plurality of tap weights and outputs a DFE signal to the second input of the summer based on the first analog signal, the digital signal and the plurality of tap weights.
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