发明名称 Embedding memory between tile arrangement of a configurable IC
摘要 Some embodiments of the invention provide a configurable IC that includes several configurable computational tiles and several memory tiles. These tiles are arranged in a particular tile arrangement. Each computational tile has a set of configurable logic circuits for configurably performing a plurality of computations and a set of configurable routing circuits. The routing circuits of the tiles configurably route signals between configurable logic circuits. The configurable IC also has several memory arrays for storing data on which the logic circuit perform computation. The memory arrays are embedded in the tile arrangement between two sets of memory tiles, where each set of memory tiles includes a set of routing circuits. In this IC, at least a first memory tile has the same set of configurable routing circuits as at least a second computational tile.
申请公布号 US7564261(B2) 申请公布日期 2009.07.21
申请号 US20070757982 申请日期 2007.06.04
申请人 发明人
分类号 H01L25/00;H03K19/177 主分类号 H01L25/00
代理机构 代理人
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