发明名称 Method and circuit for aligning data flows in time division frames
摘要 Method for aligning data flows in time division frames, providing for measuring the phase of said input data flow (DIN) with respect to the phase of a reference signal (CK), for controlling, depending on the measured phase, the delay time introduced by a delay line (VDL) in said input data flow (DIN). According to the invention, it is provided to measur e the phase of the input data flow (DIN) in a time interval substantially corresponding to the transit time of a sure data sequence containing a logic transition (AW), said sure data sequence (AW) being comprised in said input data flow (DIN). <IMAGE>
申请公布号 EP1168706(B1) 申请公布日期 2009.04.15
申请号 EP20010401565 申请日期 2001.06.15
申请人 ALCATEL LUCENT 发明人 TRAVERSO, GIOVANNI;NOVATI, MARCO;RAZZETTI, LUCA
分类号 H04L7/033;H03L7/081;H04J3/06;H04L7/04 主分类号 H04L7/033
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