发明名称 ARCHITECTURAL PHYSICAL SYNTHESIS
摘要 <p>The present invention discloses methods and apparatuses to design an integrated circuit. According to one aspect, the present invention circuit design discloses an iterative process of synthesis and placement where each iteration provides incremental changes on the design of the integrated circuit. The synthesis transform is then made with accurate timing information from the placement, and the process is incrementally iterative toward the final timing enclosure of the design. The incrementally iterative approach of the present invention provides a continuous advancement from synthesis to placement and vice versa, with the incremental improvements on synthesis made with knowledge of current instance placement, and the incremental improvements on placement made with knowledge of current circuit logic.</p>
申请公布号 WO2009014731(A9) 申请公布日期 2009.04.09
申请号 WO2008US08998 申请日期 2008.07.23
申请人 SYNOPSYS, INC.;MCELVAIN, KENNETH, S.;LEMONNIER, BENOIT;HALPIN, BILL 发明人 MCELVAIN, KENNETH, S.;LEMONNIER, BENOIT;HALPIN, BILL
分类号 G06F17/50 主分类号 G06F17/50
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