发明名称 DESIGN SUPPORT PROGRAM, COMPUTER-READABLE RECORDING MEDIUM WITH THE SAME RECORDED THEREIN, DESIGN SUPPORT DEVICE, AND DESIGN SUPPORT METHOD
摘要 PROBLEM TO BE SOLVED: To eliminate a hold error competing with a set-up error in an RC worst corner. SOLUTION: A timing analysis result analyzed by using a corner condition maximizing a time constant of a design object circuit is acquired. Thereafter, a clock net, within a clock tree related to the design object circuit, generating a hold error competing with a set-up error is detected based on the timing analysis result, and the wiring width of wiring in the clock net is changed to a wiring width larger than that of other wiring different from the wiring. COPYRIGHT: (C)2009,JPO&INPIT
申请公布号 JP2009076679(A) 申请公布日期 2009.04.09
申请号 JP20070244313 申请日期 2007.09.20
申请人 FUJITSU MICROELECTRONICS LTD 发明人 KOSUGI KAZUYUKI;GOTO MORIHARU
分类号 H01L21/82;G06F17/50 主分类号 H01L21/82
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