发明名称 LAYOUT METHOD AND LAYOUT APPARATUS
摘要 PROBLEM TO BE SOLVED: To provide a layout method providing a layout taking an EM (Electro Migration) into consideration by simple modification, and achieving a short TAT (Turn Around Time). SOLUTION: In this layout apparatus, a wiring-load-capacity-limit-value calculating part 1 calculates the limit value of a wiring load capacity from the maximum allowable current in the signal wirings of a circuit to be designed based on circuit design information when a layout wiring is arranged, and a determination part 2 determines whether or not a wiring load capacity in the signal wirings exceeds the limit value, and when the wiring load capacity exceeds the limit value, a layout correction part 3 arranges the signal wirings at a position where a wiring-load-capacity in the signal wirings is lowered below the limit value by increasing a distance between adjacent signal wirings, i.e., by reducing a wiring-load-capacity value. COPYRIGHT: (C)2009,JPO&INPIT
申请公布号 JP2009076780(A) 申请公布日期 2009.04.09
申请号 JP20070245947 申请日期 2007.09.21
申请人 FUJITSU MICROELECTRONICS LTD 发明人 USHIYAMA KENICHI
分类号 H01L21/82;G06F17/50 主分类号 H01L21/82
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