| 摘要 |
A phase locked loop (PLL) circuit including a phase comparator for comparing a phase of a reference signal with a phase of a feedback signal, an oscillator for outputting an output signal at a frequency in accordance with an output of the phase comparator, a feedback loop for returning the output signal of the oscillator and supplying the output signal as the feedback signal, and a delay circuit for delaying the phase of the output signal output from the oscillator to a load circuit, wherein the delay circuit is provided outside the feedback loop.
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