发明名称 |
CMOS integrated circuit devices having stressed NMOS and PMOS channel regions therein |
摘要 |
Methods of forming CMOS integrated circuit devices include forming at least first, second and third transistors in a semiconductor substrate and then covering the transistors with one or more electrically insulating layers that impart a net stress (tensile or compressive) to channel regions of the transistors. The covering step may include covering the first and second transistors with a first electrically insulating layer having a sufficiently high internal stress characteristic to impart a net tensile (or compressive) stress in a channel region of the first transistor and covering the second and third transistors with a second electrically insulating layer having a sufficiently high internal stress characteristic to impart a net compressive (or tensile) stress in a channel region of the third transistor. A step may then performed to selectively remove a first portion of the second electrically insulating layer extending opposite a gate electrode of the second transistor. In addition, a step may be performed to selectively remove a first portion of the first electrically insulating layer extending opposite a gate electrode of the first transistor and a second portion of the second electrically insulating layer extending opposite a gate electrode of the third transistor.
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申请公布号 |
US7800134(B2) |
申请公布日期 |
2010.09.21 |
申请号 |
US20090420936 |
申请日期 |
2009.04.09 |
申请人 |
SAMSUNG ELECTRONICS CO., LTD. |
发明人 |
LEE KYOUNG-WOO;KU JA-HUM;PARK JAE-EON |
分类号 |
H01L29/78 |
主分类号 |
H01L29/78 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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