| 摘要 |
In an internal combustion engine controller, a clock trouble determination signal from a clock trouble determining circuit that diagnoses any clock input trouble is transmitted in parallel with an abnormality diagnosis signal outputted from an abnormality diagnosing circuit and causes it to be inputted to a trouble/abnormality signal output circuit, and the trouble/abnormality signal output circuit achieves logical summing to output one line of resultant trouble/abnormality output OR signals to a microprocessor (MP). The MP outputs to the trouble/abnormality signal output circuit a trouble/abnormality confirmation input signal, and makes definite any of an abnormal state, a clock trouble state and a normal state based on the result of switching control of the status level of the pertinent trouble/abnormality output OR signal.
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