发明名称 INTEGRATED CIRCUIT MANUFACTURING/DESIGNING METHOD AND PROGRAM
摘要 <P>PROBLEM TO BE SOLVED: To improve a working speed of a circuit while suppressing an increase of power consumption as much as possible. <P>SOLUTION: A manufacturing method according to the present invention includes: calculating a threshold value from a value of a parameter that characterizes at least a part of a design pattern shape of a transistor on a target path; calculating a difference between the calculated threshold value and a target threshold value; calculating a change amount of a gate length corresponding to the difference between the threshold value and the target threshold value according to a functional relation between the threshold value of the transistor and the gate length; reducing, by the change amount, the gate length of the transistor on the target path; and manufacturing a circuit based on design information on the circuit including the transistor whose gate length is reduced. <P>COPYRIGHT: (C)2012,JPO&INPIT
申请公布号 JP2011222835(A) 申请公布日期 2011.11.04
申请号 JP20100091722 申请日期 2010.04.12
申请人 FUJITSU SEMICONDUCTOR LTD 发明人 ARIMOTO HIROSHI
分类号 H01L21/82;G06F17/50;H01L21/822;H01L27/04 主分类号 H01L21/82
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