ARCHITECTURE FOR A 3D MEMORY ARRAY

摘要

PURPOSE: A 3D memory array structure is provided to compensate the change of a threshold voltage between memory cells in an array by applying different bias conditions to a selected bit line. CONSTITUTION: An integrated circuit device includes a memory array(160) and a bias circuit. A bias circuit compensates the change of a threshold voltage corresponding to a memory state of a memory cell in an array by applying different bias conditions to the selected bit line. A row decoder(161) is connected to a plurality of word lines(162) which are arranged along a row in a memory array. A column decoder is connected to one set of page buffers(163) through a data bus.