发明名称 Voltage hold circuit
摘要 A voltage hold circuit includes four switches, an operational amplifier and a capacitor. By turning the switches on and off, the operational amplifier functions as a unity-gain buffer. In the normal operation mode, the positive input end of the operational amplifier is coupled to a node, and the output end of the operational amplifier is coupled to the capacitor. Thus the voltage of the capacitor is equal to the voltage of the node. In the power off mode, the positive input end of the operational amplifier is coupled d to the capacitor, and the output end of the operational amplifier is coupled to the node. Thus the voltage of the node is equal to the voltage of the capacitor. Therefore, the voltage hold circuit is able to hold the voltage of the node in the power down state.
申请公布号 US8330513(B2) 申请公布日期 2012.12.11
申请号 US201113050969 申请日期 2011.03.18
申请人 LAI YU-SHENG;CHANG FENG-CHIA;ETRON TECHNOLOGY, INC. 发明人 LAI YU-SHENG;CHANG FENG-CHIA
分类号 H03L7/06 主分类号 H03L7/06
代理机构 代理人
主权项
地址