发明名称 |
INTEGRATED CIRCUITS WITH CACHE-COHERENCY |
摘要 |
<p>An improved cache coherency controller, method of operation, and system of such is provided. Traffic from coherent agents to shared targets can flow on different channels through the coherency controller. This improves quality of service for performance sensitive agents. Furthermore, data transfer is performed on a separate network from coherency control. This minimizes the distance of data movement, reducing congestion for the physical routing of wires on the chip and reduces the power consumption for data transfers.</p> |
申请公布号 |
WO2013063311(A1) |
申请公布日期 |
2013.05.02 |
申请号 |
WO2012US61981 |
申请日期 |
2012.10.25 |
申请人 |
ARTERIS SAS;MOLL, LAURENT, RENE;LECLER, JEAN-JACQUES |
发明人 |
MOLL, LAURENT, RENE;LECLER, JEAN-JACQUES |
分类号 |
G06F12/00;G06F12/08 |
主分类号 |
G06F12/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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