METHOD FOR PLACING OPERATIONAL CELLS IN A SEMICONDUCTOR DEVICE

摘要

There is provided a method of placing a plurality of operational cells of a semiconductor device within a semiconductor layout, comprising determining timing data for each of the plurality of operational cells, determining switching activity from RTL or design constraints for each of the plurality of operational cells, determining power grid switch locations relative to each of the plurality of operational cells, deriving a cost function based upon the determined timing data, determined switching activity from RTL/design constraints and determined relative power grid switch locations and initially placing the plurality of operational cells according to the derived cost function.