发明名称 |
METHODS AND SYSTEMS TO SELECTIVELY BOOST AN OPERATING VOLTAGE OF, AND CONTROLS TO AN 8T BIT-CELL ARRAY AND/OR OTHER LOGIC BLOCKS |
摘要 |
Methods and systems to provide a multi-Vcc environment, such as to selectively boost an operating voltage of a logic block and/or provide a level-shifted control to the logic block. A multi-Vcc environment may be implemented to isolate a Vmin-limiting logic block from a single-Vcc environment, such as to reduce Vmin and/or improve energy efficiency in the single-Vcc environment. The logic block may include bit cells of a register file, a low-level processor cache, and/or other memory system. A cell Vcc may be boosted during a read mode and/or write wordlines (WWLs) and/or read wordlines (RWLs) may be asserted with boost. A wordline decoder may include a voltage level shifter with differential split-level logic, and a dynamic NAND, which may include NAND logic, a keeper circuit, and logic to delay a keeper control based on a delay of the level shifter to reduce contention during an initial NAND evaluation phase. |
申请公布号 |
WO2013147742(A1) |
申请公布日期 |
2013.10.03 |
申请号 |
WO2012US30627 |
申请日期 |
2012.03.26 |
申请人 |
INTEL CORPORATION;KULKARNI, JAYDEEP P.;GEUSKENS, BIBICHE M.;TSCHANZ, JAMES;DE, VIVEK K.;KHELLAH, MUHAMMAD M. |
发明人 |
KULKARNI, JAYDEEP P.;GEUSKENS, BIBICHE M.;TSCHANZ, JAMES;DE, VIVEK K.;KHELLAH, MUHAMMAD M. |
分类号 |
G11C5/14;G06F13/14;G11C8/10 |
主分类号 |
G11C5/14 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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