A multi-level cell memory includes a memory cell that stores two or more bits of information; a sensing circuit coupled to the memory cell; and a row buffer structure comprising a split page buffer having a first page buffer and a second page buffer. The sensing circuit operates to read from and write to the memory device, places a first bit in one of the first page buffer and the second page buffer, and places the second bit in one of the first page buffer and the second page buffer.
申请公布号
WO2014003755(A1)
申请公布日期
2014.01.03
申请号
WO2012US44575
申请日期
2012.06.28
申请人
HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.;MURALIMANOHAR, NAVEEN;YOON, HAN BIN;JOUPPI, NORMAN PAUL
发明人
MURALIMANOHAR, NAVEEN;YOON, HAN BIN;JOUPPI, NORMAN PAUL