发明名称 System and method for reducing lock time in a phase-locked loop
摘要 Increasing loop gain is a common practice for reducing lock time of phase locked loops. Very high loop gains, however, often result in increasing the lock time or causing loop instability. For very high loop gains, delaying the feedback clock signal along the feedback path of a phase locked loop decreases lock time and prevents instability. A delay circuit may be used at any location along the feedback path of the phase locked loop.
申请公布号 US8624685(B2) 申请公布日期 2014.01.07
申请号 US201113150860 申请日期 2011.06.01
申请人 MEI SHIZHONG;MICRON TECHNOLOGY, INC. 发明人 MEI SHIZHONG
分类号 H03B5/20 主分类号 H03B5/20
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