发明名称 MULTI-CORE PROCESSOR SYSTEM, CONTROL METHOD, AND CONTROL PROGRAM
摘要 PROBLEM TO BE SOLVED: To stop power supply at a high speed without waiting for saving of data that is stored in a volatile memory.SOLUTION: A data restoration device 110 restores, as processing of step S201, the content of a local memory onto a shared memory 104 from redundancy data after power supply to a CPU #1 and local memory 1 is stopped. Specifically, DATA 2 stored in the local memory 1 is restored using DATA 1, DATA 3, and Parity 1, and is stored in a saving area #1 within the shared memory 104. After restoration in the step S201, the data restoration device 110 reconstructs, as processing of step S202, parity data according to the number of CPUs in operation.
申请公布号 JP2014044732(A) 申请公布日期 2014.03.13
申请号 JP20130208550 申请日期 2013.10.03
申请人 FUJITSU LTD 发明人 SUZUKI TAKAHISA;YAMASHITA KOICHIRO;YAMAUCHI HIROMASA;KURIHARA YASUSHI
分类号 G06F3/06;G06F15/167;G06F15/17 主分类号 G06F3/06
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