Scalable Periphery for Digital Power Control

摘要

A scalable periphery digital power control arrangement is presented. The scalable periphery digital power control arrangement comprises a plurality of PMOS transistors connected in parallel, where the plurality of transistors is operatively coupled to a voltage source. The plurality of PMOS transistors that is operatively coupled to the voltage source can operate as a controlled current source. Current flow from the voltage source can be controlled by a logic circuit, which sends a logic signal to enable or disable each individual PMOS transistor of the plurality of PMOS transistors connected in parallel. As more PMOS transistors are enabled, the current flow through the scalable periphery digital power control arrangement to the amplifier can increase.

主权项

1. An arrangement comprising:
an amplifier; and a power control circuit operatively coupled to the amplifier and adapted to be coupled to a power source, the power control circuit comprising:
a plurality of transistors connected in parallel with one another, the plurality of transistors electrically connected between the power source and the amplifier; anda logic circuit electrically connected to each of the plurality of transistors, the logic circuit configured, during operation of the arrangement, to send a different logic signal to each transistor of the plurality of transistors to individually enable or disable each transistor of the plurality of transistors.