Phase Control Block for Managing Multiple Clock Domains in Systems with Frequency Offsets

摘要

A circuit for performing clock recovery according to a received digital signal 30. The circuit includes at least an edge sampler 105 and a data sampler 145 for sampling the digital signal, and a clock signal supply circuit. The clock signal supply circuit provides edge clock 25 and data clock 20 signals offset in phase from one another to the respective clock inputs of the edge sampler 105 and the data sampler 145. The clock signal supply circuit is operable to selectively vary a phase offset between the edge and data clock signals.

主权项

1. A circuit for receiving a digital signal comprising:
at least three samplers for sampling the digital signal, each sampler having a clock input, wherein the samplers include an edge sampler and a data sampler and an adaptive sampler; and a clock signal supply circuit for providing respective clock signals to respective clock inputs of the samplers, wherein each pair of all possible pairs of said clock signals has a relative phase between the two clock signals making up the pair, and wherein the clock signal supply circuit is operative to selectively vary the relative phase for a first pair of said clock signals and to selectively vary the relative phase for a second pair of said clock signals.