Detailed Placement with Search and Repair

摘要

A method of detailed placement for ICs is provided. The method receives an initial placement and iteratively builds sets of constraints for placement of different groups of cells in the IC design and uses a satisfiability solver to resolve placement violations. In some embodiments, the constraints include mathematical expressions that express timing requirements. The method in some embodiments converts the mathematical expressions into Boolean clauses and sends the clauses to a satisfiability solver that is only capable of solving Boolean clauses. In some embodiments, the method groups several cells in the user design and several sites on the IC fabric and uses the satisfiability solver to resolve all placement issues in the group. The satisfiability solver informs placer after each cell is moved to a different site. The method then dynamically builds more constraints based on the new cell placement and sends the constraints to the satisfiability solver.

主权项

1. A method for placement of a plurality of cells of a user design on an integrated circuit (IC), the method comprising:
building a set of timing constraints for placement of the plurality of cells on a plurality of sites on the IC; sending the set of timing constraints to a satisfiability solver; and receiving a placement that satisfies the set of timing constraints for the plurality of cells from the satisfiability solver.