| 摘要 |
A digital down converter with equalization includes an analog to digital converter (ADC), a frequency divider, an FIR-decimator-I, an FIR-decimator-Q and a frequency corrector. In operation, after some preprocessing, the FIR-decimator-I performs signal transformation equivalent to a sequence of equalization, multiplication of the processed signal by a sine wave of a conversion frequency and low pass filtering, and the FIR-decimator-Q performs signal transformation equivalent to a sequence of equalization, multiplication of the processed signal by a sine wave of conversion frequency with a phase shift of 90° and low pas filtering. The transformed signals are applied to the frequency corrector, which provides a frequency shift of predetermined value with respect to a nominal carrier frequency of the applied analog input signal and generates an In-Phase output and a Quadrature output. |
| 主权项 |
1. A digital down converter comprising:
A. an analog to digital converter (ADC) having an ADC signal input for receiving an applied analog signal, an ADC sampling clock input for receiving an applied ADC sampling clock signal characterized by a full rate (FR) clock frequency, and an ADC output, wherein the ADC is responsive to the applied analog signal and the ADC sampling clock signal to provide at the ADC output an ADC digital signal representative of the applied analog signal, B. a frequency divider (FD) having an FD input connected to the ADC sampling clock input, and an FD output, wherein the frequency divider is responsive to the ADC sampling clock to provide at the FD output a low rate (LR) clock signal characterized by an LR clock frequency corresponding to the FR clock frequency divided by a decimation factor, C. an in-phase finite impulse response filter/decimator (FIR-decimator-I) having an I-signal input connected to the ADC output, an FIR-decimator-I low frequency clock input connected to the FD output, an FIR-decimator-I sampling clock input for receiving the ADC sampling clock signal and an FIR-decimator-I output, wherein the FIR-decimator-I is responsive to the ADC digital signal, the ADC sampling clock signal and the LR clock signal, to provide at the FIR-decimator-I output, an I-transformed signal corresponding to the ADC digital signal as transformed by a sequence of equalization, multiplication of the equalized signal by a sine wave of a conversion frequency Fc with a phase shift of 0° and low pass filtering, D. a quadrature phase finite impulse response filter/decimator (FIR-decimator-Q) having a Q-signal input connected to the ADC output, an FIR-decimator-Q low frequency clock input connected to the FD output, an FIR-decimator-Q sampling clock input for receiving the ADC sampling clock signal and an FIR-decimator-Q output, wherein the FIR-decimator-Q is responsive to the ADC digital signal, the ADC sampling clock signal and the LR clock signal, to provide at the FIR-decimator-Q output a Q-transformed signal corresponding to the ADC digital signal as transformed by a sequence of equalization, multiplication of the equalized signal by a sine wave of a conversion frequency Fc with a phase shift of 90° and low pass filtering, and E. a frequency corrector (FC) having an FC-I input connected to the FIR-decimator-I output, an FC-Q input connected to the FIR-decimator-Q output, an FC-I output and an FC-Q output, wherein the frequency corrector provides an In-Phase I-output signal at the FC-I output and a Quadrature Q-output signal at the FC-Q output, and wherein a signal with the components I-output and Q-output is characterized by a frequency shift of predetermined value with respect to a nominal value of a carrier frequency of the applied analog input signal. |
