| 主权项 |
1. An apparatus for deterministic message processing in a direct memory access (DMA) adapter, the DMA adapter utilizing a first first-in-first-out (FIFO) message queue and a second FIFO message queue for processing packets received by the DMA adapter, the DMA adapter using a head pointer, a tail pointer, a sub-head pointer, and a sub-tail pointer to point to particular packets within the first FIFO message queue and the second FIFO message queue, the apparatus comprising a computer processor and a computer memory operatively coupled to the computer processor, the computer memory having disposed within it computer program instructions that, when executed by the computer processor, cause the apparatus to carry out the steps of:
incrementing from the sub-head pointer, the sub-tail pointer until encountering an out-of-sequence packet, the sub-head pointer and the sub-tail pointer pointing to packets in the first FIFO message queue; consuming packets between the sub-head pointer and the sub-tail pointer including incrementing with the consumption of each packet, the sub-head pointer until determining that the sub-head pointer is equal to the sub-tail pointer; in response to determining that the sub-head pointer is equal to the sub-tail pointer, determining that the next in-sequence packet is not in the first FIFO message queue; and in response to determining that the next in-sequence packet is not in the first FIFO message queue and that the first FIFO message queue exceeds a threshold capacity, copying the contents of the first FIFO message queue into the second FIFO message queue. |
