Methods and systems with delayed execution of multiple processors

摘要

A first first-in-first-out (FIFO) memory may receive first processor input from a first processor group that includes a first processor. The first processor group is configured to execute program code based on the first processor input that includes a set of input signals, a clock signal, and corresponding data. The first FIFO may store the first processor input and may output the first processor input to a second FIFO memory and to a second processor according to a first delay. The second FIFO memory may store the first processor input and may output the first processor input to a third processor according to a second delay. The second processor may execute at least a first portion of the program code and the third processor may execute at least a second portion of the program code responsive to the first processor input.

主权项

1. A method comprising:
receiving first processor input, at a first first-in-first-out (FIFO) memory, from a first processor group that comprises a first processor, wherein the first processor group is configured to execute program code based on the first processor input, the first processor input comprising a set of input signals, a clock signal, and corresponding data utilized for execution of the program code; storing the first processor input at the first FIFO memory; outputting the first processor input from the first FIFO memory to a second FIFO memory and to a second processor, wherein the second processor is coupled to the first FIFO memory, wherein the first processor input is output to the second processor according to a first delay; executing, at the second processor, at least a first portion of the program code responsive to the first processor input; outputting the first processor input from the second FIFO memory to a third processor coupled to the second FIFO memory, wherein the first processor input is output to the third processor according to a second delay; executing, at the third processor, at least a second portion of the program code responsive to the first processor input; extracting first information from at least one of the first processor, the second processor, and the third processor after simultaneously stopping execution of the first processor, the second processor, and the third processor, wherein the first information relates to processor system information; detecting an indicator at at least one of the first FIFO memory and the second FIFO memory, wherein the indicator is related to the execution of the program code, and wherein the simultaneously stopping execution of the first processor, the second processor, and the third processor is based on detection of the indicator; in response to the detection of the indicator, extracting second information from the at least the one of the first FIFO memory and the second FIFO memory, wherein the second information relates to contents of the at least one of the first FIFO memory and the second FIFO memory from which the second information was extracted; and performing an analysis on at least one of the first information and the second information to determine a state of execution of the program code at at least one of the second processor and the third processor.