发明名称 電子機器
摘要 <p><P>PROBLEM TO BE SOLVED: To provide an electronic apparatus which prevents reduction in the amount of data communication per unit time by reducing latency between data communications due to the clock cross over processing when the communication is performed between a first circuit unit operated based on a spread spectrum clock and a second circuit unit operated based on a PLL clock. <P>SOLUTION: A detection part 5 detects whether or not the frequency difference between a frequency of a spread spectrum clock and a frequency of a PLL clock is within a first predetermined range. When the frequency difference is within the first predetermined range, a bus bridge part 3 executes synchronous communication between a first circuit unit 1 and a second circuit unit 2, and when the frequency difference is out of the first predetermined range, the bus bridge part executes asynchronous communication between the first circuit unit 1 and the second circuit unit 2. <P>COPYRIGHT: (C)2013,JPO&INPIT</p>
申请公布号 JP5784991(B2) 申请公布日期 2015.09.24
申请号 JP20110124129 申请日期 2011.06.02
申请人 发明人
分类号 G06F13/42;G06F13/36 主分类号 G06F13/42
代理机构 代理人
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