发明名称 HV COMPLEMENTARY BIPOLAR TRANSISTORS WITH LATERAL COLLECTORS ON SOI WITH RESURF REGIONS UNDER BURIED OXIDE
摘要 Complementary high-voltage bipolar transistors in silicon-on-insulator (SOI) integrated circuits is disclosed. In one disclosed embodiment, a collector region is formed in an epitaxial silicon layer disposed over a buried insulator layer. A base region and an emitter are disposed over the collector region. An n-type region is formed under the buried insulator layer (BOX) by implanting donor impurity through the active region of substrate and BOX into a p-substrate. Later in the process flow this n-type region is connected from the top by doped poly-silicon plug and is biased at Vcc. In this case it will deplete lateral portion of PNP collector region and hence, will increase its BV.
申请公布号 US2015270335(A1) 申请公布日期 2015.09.24
申请号 US201414219760 申请日期 2014.03.19
申请人 Texas Instruments Incorporated 发明人 Sadovnikov Alexei;Babcock Jeffrey A.
分类号 H01L29/06;H01L27/082;H01L29/45;H01L27/12;H01L29/08 主分类号 H01L29/06
代理机构 代理人
主权项 1. An integrated circuit structure including both NPN and PNP high voltage transistors, comprising: complementary PNP and NPN structures; wherein the PNP and NPN structures include an SOI semiconductor structure comprising: a p-type region;active PNP and NPN device regions;a buried insulator layer BOX that lies therebetween, touches, and electrically isolates p-type region from the active PNP and NPN regions;wherein both the p-type region and the active device PNP and NPN regions are implemented with single-crystal silicon; and an n-type region is included under the buried insulator layer BOX of the PNP transistor, by implanting donor impurities through the active device region of the SOI wafer and BOX into the p-type region.
地址 Dallas TX US