发明名称 CACHE MEMORY AND PROCESSOR SYSTEM
摘要 [Problem] To provide a cache memory and a processor system which enable improved access efficiency and reduced power consumption. [Solution] A cache memory is provided with a first cache memory unit that is accessible on a cache-line-by-cache-line basis, and a second cache memory unit that is located in the same cache hierarchy as that of the first cache memory unit and is accessible on a word-by-word basis.
申请公布号 WO2015141731(A1) 申请公布日期 2015.09.24
申请号 WO2015JP58071 申请日期 2015.03.18
申请人 KABUSHIKI KAISHA TOSHIBA 发明人 TAKEDA SUSUMU;FUJITA SHINOBU
分类号 G06F12/08 主分类号 G06F12/08
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