| 摘要 |
A data processing system comprising a processor (310) comprises a plurality of cores (311-314), each core comprising a first processing pipeline and a second processing pipeline, the second processing pipeline having a different architecture to the first processing pipeline. A framework (320) is provided to configured to manage the processing resources of the data processing system including the processor. An interface (360) presents to the framework each of the processing pipelines as a cores such that each core appears as a different processor. In operation the framework may query the number of cores within the processor to indicate the number of processing pipelines so that each pipeline can be presented as a core. In one embodiment the second pipeline may be a SIMD pipeline. Further claims are directed to scheduling and compiling code to operate on the first and second pipelines when presented as a virtual processor. |
