发明名称 |
Device and method for selective reduced power mode in volatile memory units |
摘要 |
An information processing device comprises a first memory, a second memory, data transfer circuitry, power gating circuitry, and a controller. The first memory comprises at least two volatile memory units. The controller receives or generates a request for setting the information processing device into a reduced power mode; in response to the request, it selects specific memory units among the memory units; controls the data transfer circuitry to transfer data from the selected memory units to the second memory; and controls the power gating circuitry to power down the selected memory units. |
申请公布号 |
US9141178(B2) |
申请公布日期 |
2015.09.22 |
申请号 |
US201013634999 |
申请日期 |
2010.06.11 |
申请人 |
Freescale Semiconductor, Inc. |
发明人 |
Priel Michael;Rozen Anton;Smolyansky Leonid |
分类号 |
G06F1/00;G06F1/26;G06F1/32;G06F11/00;G01R31/28;G01R31/3185;G06F11/14 |
主分类号 |
G06F1/00 |
代理机构 |
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代理人 |
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主权项 |
1. An information processing device, comprising:
a first memory comprising at least two volatile memory units; a second memory; data transfer circuitry coupled to the first memory and to the second memory; power gating circuitry coupled to the first memory; and a controller programmed to: receive or generate a request for setting the information processing device into a reduced power mode; in response to the request, select specific memory units among the memory units on the basis of a desired state of the information processing device to be assumed on exiting the reduced power mode; control the data transfer circuitry to transfer data from the selected memory units to the second memory; and control the power gating circuitry to power down only the selected memory units. |
地址 |
Austin TX US |