Method and apparatus for a zero voltage processor sleep state

摘要

Embodiments of the invention relate to a method and apparatus for a zero voltage processor sleep state. A processor may include a dedicated cache memory. A voltage regulator may be coupled to the processor to provide an operating voltage to the processor. During a transition to a zero voltage power management state for the processor, the operational voltage applied to the processor by the voltage regulator may be reduced to approximately zero and the state variables associated with the processor may be saved to the dedicated cache memory.

主权项

1. A system, comprising:
a memory controller; an I/O controller; a clock generator; and a multi-core processor, the multi-core processor comprising:
a shared L2 cache memory;a memory to store a voltage identification value;a first processor core; anda second processor core; wherein the first processor core and the second processor core each support a core C6 (CC6) state in which a core state of a corresponding processor core is saved to a cache memory; and wherein the multi-core processor supports a package sleep state (C6) in which phase-locked loops (PLLs) are to be powered down and a voltage level provided to the multi-core processor is to be transitioned to a value corresponding to the voltage identification value after the first processor core and the second processor core enter the core C6 (CC6) state.