| 摘要 |
A carbon nanotube field-effect transistor encoder, based on a binary circuit which includes: a first inverter, a second inverter, a third inverter, a first three-input NAND gate, a second three-input NAND gate, a third three-input NAND gate, a fourth three-input NAND gate, a fifth three-input NAND gate, a sixth three-input NAND gate, a seventh three-input NAND gate, a first two-input NAND gate, a second two-input NAND gate, a third two-input NAND gate and a two-input AND gate. When the input end of the encoder inputs three-bit binary input signals, the three-bit binary input signals are first processed by the binary circuit; and the processed signals are input into the ternary circuit which includes a first CNFET NAND gate, a second CNFET NAND gate, a first CNFET NOR gate, a second CNFET NOR gate, a fourth inverter and a fifth inverter to be converted into ternary signals for transmission. |
| 主权项 |
1. A carbon nanotube field-effect transistor encoder, comprising a first inverter, a second inverter, a third inverter, a fourth inverter, a fifth inverter, a first three-input NAND gate, a second three-input NAND gate, a third three-input NAND gate, a fourth three-input NAND gate, a fifth three-input NAND gate, a sixth three-input NAND gate, a seventh three-input NAND gate, a first two-input NAND gate, a second two-input NAND gate, a third two-input NAND gate, a two-input AND gate, a first CNFET NAND gate, a second CNFET NAND gate, a first CNFET NOR gate, and a second CNFET NOR gate, wherein:
an input end of the first inverter, a first input end of the first three-input NAND gate, the first input end of the second three-input NAND gate, the first input end of the fourth three-input NAND gate, and the first input end of the fifth three-input NAND gate connect, and a connecting end is the first input end of the encoder which is used for accessing a first bit of a three-bit binary signal; an output end of the first inverter, a first input end of the third three-input NAND gate, and the first input end of the sixth three-input NAND gate connect; the input end of the second inverter, a second input end of the first three-input NAND gate, the first input end of the two-input AND gate, the second input end of the fourth three-input NAND gate, and the second input end of the sixth three-input NAND gate connect, and the connecting end is the second input end of the encoder which is used for accessing a second bit of the three-bit binary signal; the output end of the second inverter, the first input end of the first two-input NAND gate, the second input end of the second three-input NAND gate, the second input end of the third three-input NAND gate, and the second input end of the fifth three-input NAND gate connect; the input end of the third inverter, the second input end of the first two-input NAND gate, the second input end of the two-input NAND gate, a third input end of the third three-input NAND gate, the third input end of the fourth three-input NAND gate, and the third input end of the fifth three-input NAND gate connect, and the connecting end is the third input end of the encoder which is used for accessing a third bit of the three-bit binary input signal; the output end of the third inverter, the third input end of the first three-input NAND gate, the third input end of the second three-input NAND gate, and the third input end of the sixth three-input NAND gate connect; the output end of the first three-input NAND gate and the output end of the first two-input NAND gate are connected with the two input ends of the second two-input NAND gate respectively; the output end of the second three-input NAND gate, the output end of the third three-input NAND gate, and the output end of the fourth three-input NAND gate are connected with the three input ends of the seventh three-input NAND gate respectively; the output end of the fifth three-input NAND gate and the output end of the sixth three-input NAND gate are connected with the two input ends of the third two-input NAND gate respectively; the output end of the second two-input NAND gate is connected with the first input end of the first CNFET NAND gate; the output end of the first CNFET NAND gate is connected with the input end of the fourth inverter; the output end of the fourth inverter and the output of the two-input AND gate are connected with the two input ends of the first CNFET NOR gate respectively; the output end of the seventh three-input NAND gate is connected with the first input end of the second CNFET NAND gate; the output end of the second CNFET NAND gate is connected with the input end of the fifth inverter; the output end of the fifth inverter and the output end of the third two-input NAND gate are connected with the two input ends of the CNFET NOR gate respectively; the second input end of the first CNFET NAND gate and the second input end of the second CNFET NAND gate both access voltage signals with amplitude and electrical level corresponding to logic 1; the first inverter, the second inverter, the third inverter, the first three-input NAND gate, the second three-input NAND gate, the third three-input NAND gate, the fourth three-input NAND gate, the fifth three-input NAND gate, the sixth three-input NAND gate, the seventh three-input NAND gate, the first two-input NAND gate, the second two-input NAND gate, the third two-input NAND gate, and the two-input AND gate are all binary gate circuits; the fourth inverter and the fifth inverter are both ternary inverters; the first CNFET NAND and the second CNFET NAND gate are both ternary NAND gate circuits; the first CNFET NOR gate and the second CNFET NOR gate are both ternary NOR gate circuits; the output end of the second CNFET NOR gate is the first output end of the encoder which is used for outputting the first bit of the two-bit ternary output signal; and the output end of the CNFET NOR gate is the second output end of the encoder which is used for outputting the second bit of the two-bit ternary output signal. |
