发明名称 Reduced uncorrectable memory errors
摘要 Uncorrectable memory errors may be reduced by determining a logical array address for a set of memory arrays and transforming the logical array address to at least two unique array addresses based, at least in part, on logical locations of at least two memory arrays within the set of memory arrays. The at least two memory arrays are then accessed using the at least two unique array addresses, respectively.
申请公布号 US9136873(B2) 申请公布日期 2015.09.15
申请号 US201313792597 申请日期 2013.03.11
申请人 Intel Corporation 发明人 Pangal Kiran;Damle Prashant S.;Sundaram Rajesh;Qawami Shekoufeh;Walker Julie M.;Rivers Doyle
分类号 H03M13/00;H03M13/05;H03M13/27;G06F11/10;H03M13/15;H03M13/19 主分类号 H03M13/00
代理机构 Alpine Technology Law Group LLC 代理人 Alpine Technology Law Group LLC
主权项 1. A method to reduce uncorrectable memory errors comprising: determining a logical array address for a set of memory arrays; transforming the logical array address to at least two unique array addresses based, at least in part, on a logical location of at least two memory arrays within the set of memory arrays, wherein transforming the logical address comprises at least one of: rotating the logical array address by a number of locations based on the logical location;rotating upper lines of the logical array address by a first multiple and rotating lower lines of the logical array address by a second multiple, different than the first multiple; oradding a multiple of the logical location to the logical array address and discarding any additional upper bits; and accessing the at least two memory arrays using the at least two unique array addresses, respectively; wherein said transforming reduces uncorrectable errors in error correction codewords comprising data from the set of memory arrays.
地址 Santa Clara CA US