| 摘要 |
TSV repair circuit of a semiconductor device includes a first chip, a second chip, at least two TSV, at least two data path circuits and an output logic circuit. Each data path circuit comprises an input driving circuit, a TSV detection circuit, a memory device, a protection circuit and a power control circuit. The TSV detection circuit detects a TSV status, the memory device keeps the TSV status, the protection circuit determines whether to pull a first end of the TSV to a ground voltage according to the TSV status, and the power control circuit prevents a leakage current of a power voltage from flowing through a substrate. |
| 主权项 |
1. A through silicon repair circuit of a semiconductor device, comprising:
a first chip and a second chip, one of which stacks on the other; at least two through silicon vias, passing through a substrate of the first chip to transmit data between the first chip and the second chip; at least two data path circuits, configured in the first chip, each of which is coupled to a corresponding one of the at least two through silicon vias, wherein each of the at least two data path circuits comprises:
an input driving circuit, converting a signal input from a first signal input terminal based on a power voltage and a ground voltage and transmitting the signal to a first end of the corresponding one of the at least two through silicon vias;a through silicon via detection circuit, coupled to the first signal input terminal and the first end of the corresponding one of the at least two through silicon vias, detecting a through silicon via status of the corresponding one of the at least two through silicon vias;a memory device, receiving and keeping the through silicon via status from the through silicon via detection circuit, wherein a control terminal of the memory device is coupled to a second signal input terminal;a protection circuit, coupled to the memory device and the first end of the corresponding one of the at least two through silicon vias, determining whether or not to pull the first end of the corresponding one of the at least two through silicon vias to the ground voltage based on the through silicon via status kept by the memory device; anda power control circuit, coupled to an between the power voltage and the input driving circuit and coupled to the memory device, providing the power voltage to the input driving circuit; and an output logic circuit, configured in the second chip, generating an output signal according to signals from at least two input terminals of the output logic circuit, wherein the at least two input terminals of the output logic circuit are coupled to second ends of the at least two through silicon vias, respectively. |
