发明名称 NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD OF p-CHANNEL MOS TRANSISTOR
摘要 A non-volatile semiconductor memory device includes a memory cell transistor having a memory cell capable of writing and erasing data, and a peripheral circuit that drives the memory cell which includes a first p-channel MOS transistor including a gate electrode that is formed on a semiconductor layer with a first gate insulation film therebetween, a channel region that is formed on a surface of the semiconductor layer and has a first peak dopant concentration, a source region and a drain region that have a second peak dopant concentration higher than the first peak dopant concentration, and overlap regions that extend between the channel region and the source region and the drain region, and also below a portion of the gate electrode, that have a third peak dopant concentration higher than the first peak dopant concentration and lower than the second peak dopant concentration by one order of magnitude or more.
申请公布号 US2015255475(A1) 申请公布日期 2015.09.10
申请号 US201514630462 申请日期 2015.02.24
申请人 KABUSHIKI KAISHA TOSHIBA 发明人 Tomino Hirokazu;Noguchi Mitsuhiro
分类号 H01L27/115;H01L29/10;H01L21/28;H01L29/423;H01L21/266;H01L21/762;H01L29/08;H01L29/417 主分类号 H01L27/115
代理机构 代理人
主权项 1. A non-volatile semiconductor memory device comprising: a memory cell transistor that has a memory cell capable of writing and erasing data; and a peripheral circuit that drives the memory cell transistor, wherein the peripheral circuit has a first p-channel MOS transistor including: a gate electrode disposed on a first gate insulating film disposed on a semiconductor layer;a channel region extending on a surface of the semiconductor layer having a first peak dopant concentration;a p-type source region and a p-type drain region having a second peak dopant concentration higher than the first peak dopant concentration; andoverlap regions extending between the channel region and the source region and the drain region, and extending to the channel region in a location below the gate electrode, having a p-type third peak dopant concentration higher than the first peak dopant concentration and lower than the second peak dopant concentration by one order of magnitude or more.
地址 Tokyo JP