发明名称 半導体メモリおよびシステム
摘要 <p><P>PROBLEM TO BE SOLVED: To precharge a bit line in minimum time in the recovery from a first mode in which precharging of the bit line is stopped to a second mode, and improve an access efficiency. <P>SOLUTION: The semiconductor memory includes: a real bit line which is set at an intermediate voltage between a power source voltage and a ground voltage in a first mode in which access to a real memory cell is prohibited; a dummy bit line having the same load as that of the real bit line; a reset circuit for grounding the dummy bit line in the first mode; a first precharge circuit for connecting a first power source line to the real bit line in a second mode in which the access to the real memory cell is permitted; a second precharge circuit for connecting the first power source line to the dummy bit line in the second mode; and a detection circuit for activating a detection signal indicating the recovery to the second mode when a voltage of the dummy bit line increasing from the ground voltage exceeds the intermediate voltage, in switching from the first mode to the second mode. <P>COPYRIGHT: (C)2013,JPO&INPIT</p>
申请公布号 JP5774458(B2) 申请公布日期 2015.09.09
申请号 JP20110264478 申请日期 2011.12.02
申请人 发明人
分类号 G11C11/413;G11C11/412 主分类号 G11C11/413
代理机构 代理人
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