| 主权项 |
1. A gate driving circuit for providing a plurality of gate signals to a plurality of gate lines of a pixel array, the gate driving circuit comprising:
a shift register circuit disposed on a first side of the pixel array, the shift register circuit feeding the gate signals from the first side into the pixel array, the shift register circuit comprising:
an (N−1)th shift register stage electrically connected to an (N−1)th gate line of the gate lines, the (N−1)th shift register stage used for according to a first clock generating an (N−1)th gate signal of the gate signals;an Nth shift register stage electrically connected to an Nth gate line of the gate lines, the Nth shift register stage used for generating an Nth gate signal of the gate signals according to a second clock; andan (N+1)th shift register stage electrically connected to an (N+1)th gate line of the gate lines, the (N+1)th shift register stage used for generating an (N+1)th gate signal of the gate signals according to a third clock; and an auxiliary circuit disposed on a second side of the pixel array different from the first side, the auxiliary circuit comprising:
a first transistor having a first terminal used for receiving the second clock, a gate terminal electrically connected to the (N−1)th gate line, and a second terminal electrically connected to the Nth gate line, wherein the (N−1)th gate line is configured to turn on the first transistor when the (N−1)th gate signal is of a high level and to turn off the first transistor when the (N−1) gate signal is of a low level; anda third transistor having a first terminal used for receiving the second clock, a gate terminal electrically connected to the (N+1)th gate line, and a second terminal electrically connected to the Nth gate line; wherein N is an integer greater than 1. |
