OTP memory cell having low current leakage

摘要

A one time programmable memory cell having twin wells to improve dielectric breakdown while minimizing current leakage. The memory cell is manufactured using a standard CMOS process used for core and I/O (input/output) circuitry. A two transistor memory cell having an access transistor and an anti-fuse device, or a single transistor memory cell 100 having a dual thickness gate oxide 114 & 116, are formed in twin wells 102 & 104. The twin wells are opposite in type to each other, where one can be an N-type well 102 while the other can be a P-type well 104. The anti-fuse device is formed with a thin gate oxide and in a well similar to that used for the core circuitry. The access transistor is formed with a thick gate oxide and in a well similar to that used for I/O circuitry.

主权项

1. A memory device comprising:
a first well of a first type; a second well of a second type formed adjacent to the first well; an anti-fuse device formed over the second well with a first polysilicon gate doped to be the second type; an isolation region in the second well and adjacent to the first polysilicon gate; and, an access device formed over the first well with a second polysilicon gate for electrically coupling the anti-fuse device to a bitline contact; and a diffusion region in the first well and electrically connected to the bitline contact.