Pipelined decision feedback equalization in an interleaved serializer/deserializer receiver

摘要

An interleaved track-and-hold front-end with multiphase clocks computes and propagates unrolled decision feedback equalization results along a pipeline with the final outputs selected from one of the interleaved previous output bits with a multiplexer operating over multiple unit intervals instead of one unit interval. An n-way interleaved serializer/deserializer utilizes an n unit interval multiplexer or n one unit interval multiplexers. Pipelined decision feedback equalization allows multiple, slower multiplexers.

主权项

1. A signal processing apparatus comprising:
a first signal pipeline comprising:
a first comparator;a second comparator;a first track-and-hold element configured to receive the output from the first comparator, the first track-and-hold element configured to be driven by a first clock signal;a second track-and-hold element configured to receive the output from the second comparator, the second track-and-hold element configured to be driven by the first clock signal;a third track-and-hold element configured to receive the output from the first track-and-hold element; anda fourth track-and-hold element configured to receive the output from the second track-and-hold element; and a second signal pipeline comprising:
a first comparator;a second comparator;a first track-and-hold element configured to receive the output from the first comparator, the first track-and-hold element configured to be driven by a second clock signal; anda second track-and-hold element configured to receive the output from the second comparator, the second track-and-hold element configured to be driven by the second clock signal; and a first multiplexer configured to produce one or more feedback equalized bits.