Memory controller, storage device and error correction method

摘要

According to one embodiment, a memory controller includes an encoding unit that generates a first parity for every user data and a second parity for two or more user data and the corresponding first parity, a memory interface unit that the non-volatile memory to write and read the user data and the parities to and from the non-volatile memory, and a decoding unit that performs an error correction decoding process using the user data, and the parities. The error correction decoding processing that uses both the first parity and the second parity has at least A (a correcting capability of the first parity)+B (a correcting capability of the second parity) bits of correcting capability for the first user data and its first and second parities and for the second user data and its first and second parities.

主权项

1. A memory controller that controls a non-volatile memory, comprising:
an encoding unit that calculates a first parity from a first user data by a first error correction encoding process using a first generator polynomial, calculates a second parity from a second user data by the first error correction encoding process using the first generator polynomial, and calculates a third parity from the first user data, the first parity, the second user data, and the second parity by a second error correction encoding process using a second generator polynomial; a memory interface unit that controls the non-volatile memory to write the first user data, the first parity, the second user data, the second parity, and the third parity to the non-volatile memory; and a decoding unit that performs an error correction decoding process using the first user data, the first parity, the second user data, the second parity, and the third parity, wherein when a correcting capability of the first parity is A (A is an integer of 1 or larger) bits and a correcting capability of the third parity is B (B is an integer of 1 or larger) bits, the error correction decoding process that uses the first parity, the second parity, and the third parity has at least A+B bits of correcting capability for the first user data, the second user data, the first parity, the second parity, and the third parity.