CLOCK GENERATING CIRCUIT AND CLOCK PHASE CORRECTION METHOD

摘要

PROBLEM TO BE SOLVED: To suppress performance degradation caused by a phase variation between clocks in a clock generating circuit having a multi-phase clock output function.SOLUTION: The clock generating circuit includes: a ring oscillator part for generating a plurality of clocks having mutually different phases; a phase detector for detecting phase differences between respective two of the plurality of clocks; a load control circuit for controlling a phase of a specific clock among the plurality of clocks on the basis of respective phase differences detected by the phase detector.