| 摘要 |
<p>PROBLEM TO BE SOLVED: To provide a duty adjustment circuit which causes less deterioration in signal quality.SOLUTION: A semiconductor device comprises: a duty offset circuit 151 for creating an internal clock signal PCLKA1 with adjusted duty upon receiving an internal clock signal PCLK0; a duty offset circuit 152 for creating an internal clock signal PCLKA2 with adjusted duty upon receiving the internal clock signal PCLKA1; and a selector circuit 159 for selecting either of the internal clock signal PCLKA1 or the internal clock signal PCLKA2. According to the present embodiment, since it is possible to bypass some duty offset circuits, the number of steps of logical circuits through which the internal clock signal passes can be decreased as appropriate. This can inhibit deterioration in signal quality of the internal clock signal by the duty adjustment circuit itself.</p> |
