SHIFT REGISTER UNIT AND DISPLAY DEVICE

摘要

There are provided a shift register unit and a display device in embodiments of the present disclosure, for solving the problem that since two different transistors are used to respectively pull-up and pull-down a gate line connected to a conventional shift register unit, the conventional shift register unit occupies a large area, which causes a large consumption of materials when manufacturing the shift register unit, a high cost of the conventional shift register unit, and a high cost of a display device comprising the conventional shift register unit. The shift register unit comprises: a first capacitor, a first transistor, a pull-up module and a first pull-down module, wherein the first capacitor has a first electrode configured to receive a clock signal, a gate connected with one terminal of the first capacitor, the pull-up module and the first pull-down module, and a second electrode connected with the other terminal of the first capacitor. The first transistor in the shift register unit pull-up or pull-down the level at the gate line connected to the shift register unit.

主权项

1. A shift register unit, comprising: a first capacitor, a first transistor, a pull-up module and a first pull-down module, wherein
the first capacitor has a first electrode configured to receive a clock signal, a gate connected with one terminal of the first capacitor, the pull-up module and the first pull-down module, and a second electrode connected with the other terminal of the first capacitor; the pull-up module is configured to output a first level signal to the gate of the first transistor when the clock signal is at a second level and a pull-up selection signal is at a first level; and to not output the first level signal to the gate of the first transistor when the clock signal is at the first level and the pull-up selection signal is at the second level, wherein the pull-up selection signal is a signal output from a shift register unit one-stage previous to the shift register unit; the first pull-down module is configured to control the gate of the first transistor to be connected to a second level signal input terminal when the clock signal is at the first level and a first pull-down selection signal is at the first level, wherein the first pull-down selection signal is a signal output from a shift register unit two-stage subsequent to the shift register unit; and the first transistor is configured to output the received clock signal from the second electrode of the first transistor when a signal at the gate of the first transistor is at the first level; and to not output the received clock signal from the second electrode of the first transistor when the signal at the gate of the first transistor is at the second level.